The present invention relates to a technology for reducing a stray capacity of a diode, thus to improve the characteristic thereof.
A diode of P-i-N configuration can be produced by forming an i-type semiconductor region with extremely low impurity concentration having high resistivity between a P-type semiconductor region with high impurity concentration having low resistivity and a N-type semiconductor region with high impurity concentration having low resistivity. The diode of this PiN configuration is characterized in that a value of the resistivity between an anode and a cathode varies in response to a magnitude of current passing therethrough when it is biased in the forward direction. In addition, the diode of this PiN configuration is characterized in that, when biased in the backward direction, a depletion layer widens into the i-type semiconductor region, resulting in a capacity in the junction area to be significantly varied or a withstand voltage in the backward direction to be greater. Owing to these features, the diode of PiN configuration has been applied to a high withstand voltage rectification element, a variable resistance element or a variable capacity element.
FIG. 1 is a cross sectional view of an exemplary conventional PiN diode illustrating a main part thereof.
In this conventional PiN diode, a layer of N-type region 2 and a layer of higher resistivity region 3 are formed by deposition within a semiconductor substrate, and further a P-type region 4 is formed within the higher resistivity region 3. It should be noted that the N-type region 2 is formed so that the surface thereof is exposed in a lower face side of the semiconductor substrate. The P-type region 4 is formed so that the surface thereof is exposed in an upper face side of the semiconductor substrate while occupying a part of a region on the upper face of the semiconductor substrate. That is, the P-type region 4 is formed in the vertical direction from the upper face of the semiconductor substrate down to a predetermined depth so that the higher resistivity region 3 may be interposed between the P-type region 4 and the N-type region 2, thus to fabricate the semiconductor substrate of P-i-N configuration. Herein, the P-type region 4 serves as an anode and the N-type region 2 serves as a cathode of the diode.
An electrode 1 is arranged on the top of the N-type region 2, which is exposed in the lower face side of the semiconductor substrate. A dielectric layer 5 is formed over the upper face of the semiconductor substrate excluding a central portion of the exposed surface of the P-type region 4. An electrode 6 is arranged to cover the exposed surface of the P-type region 4 and a part of an upper face of the dielectric layer 5. It should be noted that the electrode 6 is electrically connected to the P-type region 4 in the exposed surface of the P-type region 4. A wire 7 is bonded to the upper face of the electrode 6.
Herein, the higher resistivity region 3 is treated as an intrinsic semiconductor (i) region, and for this reason, the diode with the configuration as illustrated in FIG. 1 is called a PiN diode. However, due to the various circumstances, it has been frequently observed that this higher resistivity region 3 has turned to be a N-type semiconductor doped with extremely little amount of N-type impurities and having fewer carriers.
In the diode having the PiN configuration as shown in FIG. 1, assume the case where a positive voltage is applied to the electrode 6 and a negative voltage to the electrode 1. That is to say, assume that a forward voltage is applied between the anode and cathode of the diode.
Since the impurity concentration in the higher resistivity region 3 is extremely low, inherently the resistivity value of the higher resistivity region 3 is high in accordance with the intrinsic semiconductor. However, when the forward voltage is applied to the diode, electrons, majority carriers in the N-type semiconductor, are injected into the higher resistivity region 3 from the N-type region 2. Accordingly, the concentration of carriers within the higher resistivity region 3 increases and the resistivity value of the higher resistivity region 3 decreases. In the view that a current is a stream of electrons, the more forward current passes between the anode and cathode of the diode, the more electrons are injected into the higher resistivity region 3 from the N-type region 2. As a result, the resistivity value of the higher resistivity region 3 changes in response to the magnitude of the forward current, and this PiN diode exhibits a negative relation between current and resistance as shown in FIG. 2.
In contrast with this, assume the case where a negative voltage is applied to the electrode 6 and a positive voltage to the electrode 1 in FIG. 1. That is to say, assume that a backward voltage is applied between the anode and the cathode of the diode.
When the negative voltage is applied to the electrode 6, a depletion layer is created in a part of the P-type region 4 and inside the higher resistivity region 3. At that time, a junction capacity is generated between the P-type region 4 and the higher resistivity region 3 each being disposed in an opposite side from other with respect to the depletion layer, respectively. It should be noted that, if the depletion layer widens over an entire area of the higher resistivity region 3, the junction capacity is generated between the P-type region 4 and the N-type region 2 each being disposed in an opposite side from other with respect to the higher resistivity region 3 respectively. Herein, since the higher resistivity region 3 has a lower concentration of impurities, the number of carriers (electrons, or holes) per unit volume in the higher resistivity region 3 is much less in comparison with that in the N-type region 2. Owing to this, the depletion layer within the higher resistivity region 3 changes its formation region significantly in response to a slight change in the backward voltage. The junction capacity of the diode is subject to change according to a state of the depletion layer, in particular a thickness of the depletion layer. Because of this, the diode of PiN configuration is characterized in that the junction capacity thereof varies in response to the change of voltage.
In recent years, a frequency of a signal processed in an electronic device has been much higher than the frequency used in the past. If the higher frequency of the signal is used, a smaller value of an electrostatic capacity of a capacitive element is required, as could be seen from, for example, a relational expression defined as 1/f=2xcfx80(LC)xc2xd. When the diode is used as a variable capacitive element, an area of the PN junction must be reduced in order to make the capacity value thereof smaller. In practice, in order to reduce the capacity value of the diode with the configuration as shown in FIG. 1, the P-type region 4 must be formed to be as small as possible.
By the way, a diameter of a contact portion 7a, which will be created in the tip of a wire 7 for wiring when the wire 7 is bonded to the electrode 6, could expand to be about three times as big as the diameter of the wire 7. Because of this, the electrode 6 must have been formed much larger than the possible diameter of the contact portion 7a. Accordingly, a projected area of the electrode 6 onto the upper face of the semiconductor substrate should be larger than the area of the P-type region 4 and thereby the electrode 6 has to be partially expanded outwardly along a plane direction of the substrate beyond the P-type region 4. As a result, a capacity other than the junction capacity, what is called a stray capacity, would be generated between the electrode 6 and the higher resistivity region 3 each being disposed in opposite side from other placing the dielectric layer 5 therebetween. A total value of this stray capacity and the junction capacity would make a substantial capacity value of the variable capacity element. Therefore, there has been a problem that a minimum capacity value possible to be set for the variable capacity element becomes greater by the stray capacity being added to the junction capacity.
Further, when the backward voltage is applied between the anode and the cathode, disadvantageously the depletion layer would be formed also in the vicinity of the surface of the higher resistivity region 3 lying under the electrode 6 by an electrostatic inductive action of the negative voltage applied to the electrode 6, as shown in FIG. 3. Thus, there has been a problem that a ratio of a maximum value to a minimum value for an available capacity of the variable capacity element is limited to be smaller by the undesired depletion layer formed in the vicinity of the surface of the higher resistivity region 3 and by said stray capacity added to the capacity value of the diode. By the way, this ratio of the maximum value to the minimum value for the available capacity is generally referred to as a rate of change.
On the other hand, when the diode of PiN configuration is used as a variable resistance element, preferably a current-resistance characteristic between the anode and the cathode should change linearly. Further, a resistance value occurring between the anode and the cathode when the forward current being small is preferably as high as possible. However, the actual resistance value, which occurs between the anode and the cathode, is lower than an ideal characteristic (a straight line) in a range of smaller forward current, as shown in FIG. 2. Thus, this has caused another problem that, as larger stray capacity occurs between the anode and the cathode, the resistance value between the anode and the cathode in the range of smaller forward current becomes lower comparing with the value for the ideal characteristic.
In the light of the problems described above, an object of the present invention is to provide a diode which can reduce a stray capacity to improve various characteristics thereof.
The object described above could have been accomplished by an inventive diode having an anode region made up of P-type semiconductor and a cathode region made up of N-type semiconductor each formed within a semiconductor substrate, said diode comprising: said anode region formed such that a surface thereof is exposed on a predetermined face of the semiconductor substrate while occupying a part of a region on a predetermined face; an electrode arranged on the surface of said anode region so as to be connected therewith; and a conductive layer which is partially interposed between the electrode and the semiconductor substrate, is isolated from the electrode by a dielectric layer, and is connected with the semiconductor substrate in a predetermined location.
In practice, a diode according to the present invention employs a configuration as described below.
A P-type region, a N-type region and a higher resistivity region are formed within a semiconductor substrate, thus to make a P-i-N configuration. Herein, P-type region is formed so that the surface thereof is exposed in the upper face side of the semiconductor substrate so as to occupy a part of the region on the upper face of the semiconductor substrate. Further, the P-type region is formed in the vertical direction from the upper face of the semiconductor substrate to a level of predetermined depth. The N-type region is formed so that the surface thereof is exposed in the lower face side of the semiconductor substrate. The higher resistivity region is formed so as to be interposed between the P-type region and the N-type region. A dielectric layer, a conductive layer and a second dielectric layer are formed by deposition in this order on the upper face of the semiconductor substrate excluding a central portion of the exposed surface of the P-type region. Then, an electrode is formed so as to be connected with the P-type region, also covering a range from the exposed surface of the P-type region to the upper face of the second dielectric layer.
Herein, the conductive layer is formed so that it is isolated from the electrode by the second dielectric layer, is connected with the semiconductor substrate upper face in a location where the dielectric layer has not been formed, and resides at least partially in a location sandwiched between the electrode and the semiconductor substrate. Preferably, the conductive layer is formed so as to be necessarily interposed between the electrode and the semiconductor substrate, and the conductive layer is connected with the semiconductor substrate upper face in a location more distant from the outer edge portion of the electrode with respect to the P-type region. More preferably, when the semiconductor substrate is fabricated, a lower resistivity region made up of N-type semiconductor should be formed in the junction area of the semiconductor substrate, where the semiconductor substrate is to be connected with the conductive layer, so that the surface of the N-type semiconductor is exposed on the upper face of the semiconductor substrate.